In one aspect, the present application specifies an optoelectronic semiconductor chip having an improved overall electro-optical efficiency.
An optoelectronic semiconductor chip is specified comprising a semiconductor layer sequence having an active layer provided for generating radiation between a layer of a first conductivity type and a layer of a second conductivity type.
By way of example, the layer of the first conductivity type is an n-conducting layer. The layer of the second conductivity type is then a p-conducting layer. As an alternative, the layer of the first conductivity type can also be a p-conducting layer and the layer of the second conductivity type can also be an n-conducting layer.
The active layer preferably contains a pn junction, a double heterostructure, a single quantum well (SQW) or a multi quantum well structure (MQW), for generating radiation. In this case, the designation quantum well structure does not exhibit any significance with regard to the dimensionality of the quantization. It therefore encompasses, inter alia, quantum wells, quantum wires and quantum dots and any combination of these structures. Examples of MQW structures are described in the documents WO 01/39282, U.S. Pat. No. 5,831,277, U.S. Pat. No. 6,172,382 B1 and U.S. Pat. No. 5,684,309, the disclosure content of which in this respect is hereby incorporated by reference.
The layer of the first conductivity type is adjacent to a front side of the semiconductor layer sequence. The layer of the second conductivity type is adjacent, in particular, to a rear side of the semiconductor layer sequence. The rear side of the semiconductor layer sequence is arranged in a manner lying opposite the front side. The semiconductor chip is provided, in particular, for the emission of an electromagnetic radiation generated by the active layer from its front side.
In accordance with at least one embodiment, the semiconductor layer sequence contains at least one cutout extending from the rear side of the semiconductor layer sequence through the active layer to the layer of the first conductivity type.
The cutout therefore constitutes a depression extending into the semiconductor layer sequence from the rear side in the direction of the front side. In one configuration, the depression has the form of a blind hole. The cutout has, for example, a central axis running perpendicularly or obliquely with respect to a main extension plane of the semiconductor layer sequence. The cutout expediently runs through the layer of the second conductivity type and the active layer. The cutout extends, in particular, from the rear side into the layer of the first conductivity type and preferably ends in a central region of the layer of the first conductivity type.
In this embodiment, the layer of the first conductivity type is electrically connected through the cutout by means of a first electrical connection layer, which covers the rear side of the semiconductor layer sequence at least in places. Expediently, in the cutout, the first electrical connection layer is electrically insulated from the active layer and the layer of the second conductivity type by means of an electrical isolation layer.
The fact that the first electrical connection layer covers the rear side of the semiconductor layer sequence at least in places means in the present case that at least one part of the first electrical connection layer succeeds the semiconductor layer sequence in a direction from the front side toward the rear side. However, it is not necessary for the entire first electrical connection layer to be arranged at the rear side. Rather, a partial region of the first electrical connection layer extends from the rear side into the cutout as far as the layer of the first conductivity type. In particular, the first electrical connection layer adjoins the semiconductor layer sequence in the region of the cutout. The first electrical connection layer is a metallic layer, for example, that is to say that it comprises a metal or a plurality of metals or consists thereof. It is provided for feeding an electric operating current to the semiconductor layer sequence.
If the layer of the first conductivity type has a central region, the latter constitutes a current distribution layer, for example. For this purpose, it can have an increased dopant concentration, for example. By way of example, the concentration of a dopant of the first conductivity type in the central layer is five times, in particular, 10 times, as high as in a partial region of the layer of the first conductivity type which adjoins the central region in the direction of the front side and/or in the direction of the rear side. As an alternative or in addition, the central region can have a superlattice of alternating layers. In the case of such a superlattice, the layers, for example, alternating GaN and AlGaN layers, have in one configuration a layer thickness of less than or equal to 10 nm, preferably of less than or equal to 5 nm, and in particular of less than or equal to 2 nm. It may be provided that in each case one of the alternating layers is doped with a dopant of the first conductivity type and the other layer is nominally undoped.
In this embodiment, the semiconductor chip contains, in the region of the cutout, a junction layer having a material composition composed of material of the layer of the first conductivity type and composed of material of the first electrical connection layer. In particular, the cutout and the junction layer overlap laterally.
The fact that the junction layer has a material composition composed of material of the layer of the first conductivity type and composed of material of the first electrical connection layer is understood to mean in the present context, in particular, that the material of the layer of the first conductivity type and the material of the first electrical connection layer are mixed with one another. Preferably, the junction layer has a uniform material composition, for example, in the manner of an alloy, between the material of the layer of the first conductivity type and the material of the first electrical connection layer. In this case, it is possible for the proportion of the material of the first electrical connection layer to decrease continuously or in steps over the layer thickness of the junction layer in the course from the rear side to the front side. By way of example, the material of the first electrical connection layer is indiffused into the material of the layer of the first conductivity type.
A particularly low electrical contact resistance between the first electrical connection layer and the layer of the first conductivity type is advantageously obtained by means of the junction layer. Preferably, the contact resistance is less than or equal to 2×10−5 ohms/cm2, for example, approximately 2×10−6 ohms/cm2. A low contact resistance is advantageous particularly during operation of the semiconductor chip with a high operating current, for instance of 1 A or more, for example, of 1.4 A or more. At high operating currents, the contact resistance can dominate the characteristic curve of the semiconductor chip.
In one configuration of this embodiment, a maximum lateral extent of the cutout is greater than or equal to 10 μm. In another configuration, the maximum lateral extent of the cutout is less than or equal to 30 μm.
In a further configuration, the semiconductor chip has a plurality of cutouts having a lateral distance from one another of greater than or equal to 75 μm. In a further configuration, the lateral distance is less than or equal to 125 μm. It preferably has a value of between 75 μm and 125 μm, inclusive of the limits. In this case, the lateral distance of the cutouts from one another is the distance between respectively two laterally successive cutouts.
In one configuration, a total area of the cutouts in a plan view of the rear side is less than or equal to 5 percent, in particular, less than or equal to 2 percent of the rear-side main area of the semiconductor layer sequence. The rear-side main area is that part of the surface of the semiconductor layer sequence which faces the rear side.
Therefore, such a small total area of the cutouts is advantageous for the optical efficiency of the semiconductor chip. Conventional semiconductor chips often have an electrical connection area which covers ten percent or more of a main area of the semiconductor layer sequence. In the present case, the area of the electrical connections of the layer of the first conductivity type is predefined by the area of the cutouts. The loss of active area due to the electrical connections of the layer of the first conductivity type is particularly small in this way. Despite such a small electrical connection area, a comparatively low electrical contact resistance between the semiconductor layer sequence and the first electrical connection layer can nevertheless be obtained by means of the junction layer.
In another embodiment, the optoelectronic semiconductor chip has, as an alternative or in addition to a first electrical connection layer, by means of which the layer of the first conductivity type is connected through a cutout, a second electrical connection layer, which covers the rear side of the semiconductor layer sequence at least in places. The layer of the second conductivity type is electrically connected by means of the second electrical connection layer.
The first electrical connection layer and the second electrical connection layer are electrically insulated from one another, in particular, by means of an electrical isolation layer. In one preferred configuration, the first electrical connection layer, the second electrical connection layer and the electrical isolation layer overlap laterally at the rear side of the semiconductor chip.
In such a configuration, by way of example, the light-emitting front side of the semiconductor chip is free of electrical contact locations such as bonding pads. The risk of shading and/or absorption of part of the electromagnetic radiation emitted by the active layer during operation by the electrical contact locations can be reduced in this way.
In one development of this embodiment, the semiconductor chip has an electrically insulating mirror layer at the rear side of the semiconductor layer sequence. The electrically insulating mirror layer has a plurality of openings through which the layer of the second conductivity type is electrically connected by means of the second electrical connection layer. In particular, therefore, the electrically insulating mirror layer is arranged at least in places between the semiconductor layer sequence and the first and/or second electrical connection layer. Instead of an electrically insulating mirror layer, a semiconducting mirror layer can also be provided.
A refractive index of the mirror layer deviates, for example, by 1 or more from the refractive index of a layer of the semiconductor layer sequence which succeeds the mirror layer in the direction of the front side and, in particular, adjoins the latter. In one configuration, the mirror layer contains a dielectric such as SiO2 or silicon nitride (SiNx). In one development, the electrically insulating mirror layer contains a distributed Bragg reflector (DBR) containing at least one pair of layers having alternately high and low refractive indices. The layers of the Bragg reflector contain, for example, silicon dioxide, tantalum dioxide and/or titanium dioxide.
The electrically insulating mirror layer has, for example, on account of the change in the refractive index, a particularly high reflection coefficient, such that it reflects electromagnetic radiation emitted by the active layer in the direction of the rear side back in the direction of the front side particularly efficiently.
In one configuration, the electrically insulating mirror layer contains at least one low refractive index material. In the present case, a low refractive index material is understood to mean a material having a refractive index of less than or equal to 1.38, preferably of less than or equal to 1.25.
Such a low refractive index material comprises, for example, a matrix material containing pores. The matrix material can be silicon dioxide, for example. The pores are filled, in particular, with a gas, for instance air. The matrix material has, for example, a refractive index that is greater than the refractive index of the gas. By virtue of the pores, the effective refractive index of the low refractive index material is lowered below the refractive index of the matrix material. The pores have, in particular, extents in the nanometers range, for example, of less than or equal to 8 nm, preferably of less than or equal to 3 nm.
A particularly high critical angle of total reflection is advantageously obtained with the low refractive index material. Even light beams which impinge comparatively steeply on the electrically insulating mirror layer are thus totally reflected by means of the low refractive index material.
In one development, the low refractive index material additionally has a dielectric constant of less than or equal to 3.9, preferably of less than or equal to 2.7. By way of example, a low refractive index material having a dielectric constant of less than or equal to 3.9, and in particular, of less than or equal to 2.7, absorbs only comparatively little electromagnetic radiation in the case of a layer thickness in the range of up to a few 100 nanometers. Preferably, the absorption coefficient of the electrically insulating mirror layer is less than or equal to 10−3.
Instead of pores or in addition to the pores, the low refractive index material can also contain one or more additives. By way of example, fluorine, chlorine or C-H are suitable additives for silicon dioxide. In particular, these substances occupy binding sites at the silicon and thus prevent the formation of a fully crystalline network composed of silicon dioxide.
A low refractive index material having pores can be produced, for example, by such additives being driven out again from the matrix material by means of a suitable process, for example, by heating. In the case of silicon dioxide, by way of example, a low refractive index material having a refractive index of approximately 1.14 can be obtained in this way.
In one configuration, the electrically insulating mirror layer covers at least 50 percent of the rear-side main area of the semiconductor layer sequence. It preferably reflects at least 96 percent of the light impinging on it back in the direction of the front side.
The electrically insulating mirror layer can also have a refractive index of less than 1 or, for a predefined frequency range, even a refractive index of less than 0. A mirror layer of this type can be realized by means of a photonic crystal, for example. By means of a three-dimensional photonic crystal, for example, a total reflection of the electromagnetic radiation emitted by the active layer can be obtained independently of the angle of incidence on the electrically insulating mirror layer. For this purpose, the periods of the three-dimensional photonic crystal are, for example, at a quarter of the wavelength of an emission maximum of the active layer.
In one advantageous configuration, the electrically insulating mirror layer has, in the direction from the front side to the rear side, firstly a layer comprising a low refractive index material and then a Bragg reflector. By means of the layer comprising the low refractive index material, electromagnetic radiation which is emitted by the active layer and which impinges on the mirror layer at a comparatively shallow angle is reflected back by total reflection to the front side. Electromagnetic radiation which is emitted by the active layer and which impinges on the mirror layer at a steep angle, for example, perpendicularly, is transmitted by the layer comprising the low refractive index material and is reflected back to the front side by the Bragg reflector, which has a high reflection coefficient, in particular, for steeply impinging electromagnetic radiation.
In a further advantageous configuration, the optoelectronic semiconductor chip contains a further junction layer between the second electrical connection layer and the layer of the second conductivity type, the further junction layer having a material composition composed of material of the layer of the second conductivity type and material of the second electrical connection layer.
In one variant of the semiconductor chip, the layer of the second conductivity type is electrically connected indirectly by means of the second electrical connection layer. In particular, the layer of the second conductivity type, if appropriate the further junction layer and the second electrical connection layer do not succeed one another directly in the case of this variant. In one development of this variant, the semiconductor layer sequence contains a tunnel junction and a further layer of the first conductivity type, which succeed the layer of the second conductivity type in this order toward the rear side. Examples of such a semiconductor layer sequence, for instance an npn-semiconductor layer sequence are described in the document WO 2007/012327 A1, the disclosure content of which in this respect is hereby incorporated by reference. In the case of a semiconductor chip in accordance with this development which has a further junction layer, the further junction layer contains material of the further layer of the first conductivity type instead of material of the layer of the second conductivity type.
In another configuration of the semiconductor chip, the openings of the electrically insulating mirror layer have a maximum lateral extent, that is to say, by way of example, a diameter in the case of circular holes or a diagonal in the case of rectangular holes, of less than of equal to 1 μm. Laterally successive openings have a lateral distance of less than or equal to 5 μm.
In particular in the case of a further junction layer between the second electrical connection layer and a layer of the second conductivity type which is a p-conducting layer, the operating current can be impressed into the p-conducting layer particularly homogeneously in this way. It is particularly advantageous if a ratio between a distance between two adjacent openings and a maximum lateral extent of the openings or of at least one of the openings is less than or equal to 10.
In one configuration, the junction layer and/or the further junction layer have/has a layer thickness, that is in the present case, in particular, the extent thereof in the direction from the rear side to the front side, of greater than or equal to 5 nm, for example, of greater than or equal to 10 nm.
The first and/or the second electrical connection layer comprise(s), for example, at least one of the following materials: Au, Ag, Al, Cr, Cu, Ti, Pt, Ru, NiAu.
In one configuration, the first and/or the second electrical connection layer have/has a multilayer structure. In one development, the multilayer structure contains a layer facing the semiconductor layer sequence and comprising Cr, Ti, Pt, Ru and/or NiAu. A layer of the multilayer structure which is remote from the semiconductor layer sequence can comprise, for example, Al, Ag, Au and/or Cu.
By way of example, a particularly good adhesion of the first and/or the second electrical connection layer to the semiconductor layer sequence and/or the insulating mirror layer can be obtained by means of the layer facing the semiconductor layer sequence. The layer remote from the semiconductor layer sequence has, for example, a particularly good electrical conductivity and/or a particularly high reflection coefficient.
In one advantageous configuration, the layer of the multilayer structure which faces the semiconductor layer sequence is light-transmissive. By way of example, it comprises NiAu. NiAu becomes light-transmissive, in particular, as a result of heating in an oxygen-containing atmosphere. As an alternative or in addition, the layer of the multilayer structure which faces the semiconductor layer sequence can also be light-transmissive on account of its layer thickness. A light-transmissive layer of the multilayer structure which faces the semiconductor layer sequence is advantageous, in particular, if the layer of the multilayer structure which is remote from the semiconductor layer sequence has a particularly high reflection coefficient.
In one configuration, the junction layer contains material of the layer facing the semiconductor layer sequence, that is to say Ti, Pt and/or NiAu. As an alternative or in addition, however, it can also comprise material of the layer remote from the semiconductor layer sequence, that is to say, for example, Al, Ag and/or Au. The material of the layer of the multilayer structure which is remote from the semiconductor layer can pass into the junction layer through the layer facing the semiconductor layer sequence, for example, during the production of the optoelectronic semiconductor chip.
In a further configuration, the optoelectronic semiconductor chip is a thin-film light emitting diode chip. In particular, it has a carrier plate at its rear side. In one configuration, the first and the second electrical connection layers are arranged at least in places between the semiconductor layer sequence and the carrier substrate.
A thin-film light emitting diode chip is distinguished by at least one of the following characteristic features:                a reflective layer is applied or formed at a main area, facing a carrier element, in particular the carrier plate, of the radiation-generating semiconductor layer sequence, which is a radiation-generating epitaxial layer sequence, in particular, which reflective layer reflects at least part of the electromagnetic generated in the semiconductor layer sequence back into the latter. At least one partial region of the reflective layer is formed, for example, by the electrically insulating mirror layer and/or by the first and/or the second electrical connection layer;        the thin-film light emitting diode chip has a carrier element, which is not a growth substrate on which the semiconductor layer sequence was grown epitaxially, but rather a separate carrier element that was subsequently fixed to the semiconductor layer sequence;        the semiconductor layer sequence has a thickness in the range of 20 μm or less, in particular, in the range of 10 μm or less;        the semiconductor layer sequence is free of a growth substrate. In the present case, “free of a growth substrate” means that a growth substrate used, if appropriate, for the growth process is removed from the semiconductor layer sequence or at least greatly thinned. In particular, it is thinned in such a way that it is not self-supporting by itself or together with the epitaxial layer sequence alone. The remaining residue of the greatly thinned growth substrate is, in particular, unsuitable as such for the function of a growth substrate; and        the semiconductor layer sequence contains at least one semiconductor layer with at least one area having an intermixing structure which ideally leads to an approximately ergodic distribution of the light in the semiconductor layer sequence, that is to say that it has, as far as possible, ergodically stochastic scattering behavior.        
A basic principle of a thin-film light emitting diode chip is described, for example, in the document I. Schnitzer et al., Appl. Phys. Lett. 63 (16) Oct. 18, 1993, pages 2174-2176, the disclosure content of which in this respect is hereby incorporated by reference. Examples of thin-film light emitting diode chips are described in the documents EP 0905797 A2 and WO 02/13281 A1, the disclosure content of which in this respect is hereby likewise incorporated by reference.
A thin-film light emitting diode chip is to a good approximation a Lambertian surface emitter and is therefore well suited, for example, to application in a headlight, for instance a motor vehicle headlight.
In a method for producing an optoelectronic semiconductor chip, in one configuration, the semiconductor layer sequence having the cutout is provided. Afterward, the first electrical connection layer is deposited onto at least one partial region of a surface of the cutout. As an alternative, it is possible firstly for only a part of the first electrical connection layer to be deposited on at least one partial region of the surface of the cutout. For example, in the case of a first electrical connection layer having a multilayer structure, it is possible for only one of the layers, which, in the completed semiconductor chip, constitutes the layer facing the semiconductor layer sequence, to be deposited. The deposition can be effected by means of an evaporation method, for example.
At the same time as the deposition or after the deposition of the first electrical connection layer or of the part of the first electrical connection layer, in the method, the semiconductor layer sequence and the first electrical connection layer or the part of the first electrical connection layer are heated in such a way that material of the first electrical connection layer penetrates into the semiconductor layer sequence through the surface of the cutout in order to form the junction layer. By way of example, the heating constitutes a sintering process. The material of the first electrical connection layer can penetrate into the semiconductor layer sequence by means of diffusion, for example.
In one configuration, the material of the first electrical connection layer is a eutectic. A eutectic advantageously has a particularly low melting point. In one configuration of the method, the material of the first electrical connection layer is melted at least in places during heating.
In one configuration, the heating of the semiconductor layer sequence and of the first electrical connection layer or respectively of the part of the electrical connection layer is effected at a temperature of greater than or equal to 350° C., in particular, greater than or equal to 400° C. The temperature is preferably less than or equal to 800° C., in particular, less than or equal to 500° C. In one configuration, the first electrical connection layer or the part of the first electrical connection layer is heated in oxygen gas or an oxygen-containing gas mixture.
In a further configuration of the method, a second electrical connection layer or a part of a second connection layer is deposited onto the semiconductor layer sequence. The deposition of the second electrical connection layer can be effected at the same time as the deposition of the first electrical connection layer, before the deposition of the first electrical connection layer or after the deposition of the first electrical connection layer.
In one development of this configuration, before the deposition of the second electrical connection layer, an electrically insulating mirror layer provided with openings is applied onto the rear side of the semiconductor layer sequence. The second electrical connection layer or the part of the second electrical connection layer is expediently deposited onto the semiconductor layer sequence at least in the region of the openings.
Afterward, the semiconductor layer sequence and the second electrical connection layer or the part of the second electrical connection layer are heated in such a way that material of the second electrical connection layer penetrates into the semiconductor layer sequence, in particular, in the region of the openings of the electrically insulating mirror layer in order to form the junction layer.
The heating of the second electrical connection layer can be effected at the same time as, before or after the heating of the first electrical connection layer or respectively of the part of the first electrical connection layer. The temperature is once again preferably greater than or equal to 350° C., in particular, greater than or equal to 400° C. and/or less than or equal to 800° C., in particular, less than or equal to 600° C. The heating can be effected in oxygen gas or in an oxygen-containing gas mixture.
In one configuration of the method, the first electrical connection layer or a part thereof is deposited and heated to a first temperature. Before or after this, the second electrical connection layer or a part thereof is deposited and heated to a second temperature, wherein the second temperature differs from the first temperature. In this configuration, the method is preferably carried out in such a way that firstly that electrical connection layer which is heated to the higher of the two temperatures is deposited and heated.
In a further configuration of the method, the semiconductor layer sequence provided has a growth substrate, which is removed in a subsequent method step, that is to say in a method step which follows the heating of the semiconductor layer sequence with the first and/or second electrical connection layer. In this configuration, it may be provided that the semiconductor layer sequence is fixed to a carrier plate before or after the removal of the growth substrate. This can be effected by means of a eutectic bonding step, a solder connection and/or an adhesive connection, for example.
In this configuration of the method, the first electrical connection layer and/or the second electrical connection layer are/is produced before the connection of the semiconductor layer sequence to the carrier plate. In this way, it is possible, during the production of the electrical connection layers, to heat the semiconductor chip to temperatures which are higher than the temperature up to which the connection between the semiconductor layer sequence and the carrier plate remains stable, and which are necessary for forming the junction layer(s).